Accurate power detection for a multi-stage amplifier

ABSTRACT

A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional PatentApplication Serial No. 60/424,526, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field

[0003] The present disclosure relates to amplifiers having a pluralityof amplifier stages, and in particular to methods and structures fordetecting the output power of such amplifiers.

[0004] 2. Discussion of the Related Art

[0005] Power detectors are used in radio frequency (RF) communicationssystems to monitor the power of an RF signal that is output to anantenna. The power detector produces a direct current (DC) signal thatis proportional to the power of the RF signal being sampled. Thecommunications system can then use the DC signal as a measure of thepower of the RF signal being transmitted, and can make adjustments inorder to maintain the output power within system specifications.

[0006] Conventional power detection techniques sample the RF signalimmediately before the antenna, after a final amplifier stage of amulti-stage amplifier amplifies the RF signal and after the RF signalpasses through a final matching network between the final amplifierstage and the antenna. However, under conditions where the amplifierload is not impedance matched properly, which may be due to a faulty orbroken antenna or to environmental conditions, the voltage monitored bythe power detector can be in error, in that the voltage no longeraccurately predicts the true output power. Depending upon theconditions, the detector could overestimate or underestimate the actualpower.

[0007] An underdetection of the output power could have seriousconsequences. For instance, the communications system may work toincrease the output power by further amplifying the RF signal, based onthe erroneous information that the output power is too low. Thecommunications system might then increase the output power beyond a safeor regulated level. Outputting too much power could lead to a violationof health regulations, a danger to users, lawsuits, and the like. Inaddition, the efficiency of the communications system would be reduced,since the communications system would be expending more energy thannecessary to amplify the outgoing RF signal. Such would be particularlyproblematic in wireless applications, such as cellular phones, thatoperate on battery power. The battery power reserve could be needlesslydepleted.

[0008] Therefore, there exists a need to accurately measure the power ofan RF signal amplified by a multi-stage amplifier, and to avoidunderdetecting the power of the RF signal.

SUMMARY OF THE DISCLOSURE

[0009] Embodiments of the present invention include a method, system andcircuit for accurately determining the power of signals amplified by amulti-stage amplifier.

[0010] In one embodiment, a multi-stage amplifier is provided in asignal path. The multi-stage amplifier amplifies a signal, which may bean RF signal, that passes through the signal path. A power detector iscoupled to the signal path at an interior node of the multi-stageamplifier, and samples the signal at the interior node.

[0011] Most broadly, the interior node is between, but exclusive of, theinput and output nodes of the multistage amplifier. More particularly,the interior node may be between the output node of a first amplifierstage and the output node of a last amplifier stage of the multi-stageamplifier, excluding the output node of the final amplifier stage. Evenmore particularly, the interior node is between, and inclusive of, theoutput node of the first amplifier stage and an input node of the finalamplifier stage.

[0012] The power detector samples the signal at the selected interiornode of the multi-stage amplifier, and outputs a feedback signal thatreflects the power of the signal at the interior node. A processor orother control circuit receives the feedback signal from the powerdetector, and initiates an adjustment so that the amplified signaloutput by the multi-stage amplifier is at the proper power level.

[0013] In an alternative embodiment, a power detector may sample thesignal at a plurality of interior nodes, and may output a feedbacksignal to the processor that reflects a sum of the power as theplurality of interior nodes.

[0014] In a further embodiment, a wireless communications devicecomprises a baseband processor, a multi-stage amplifier, and an antenna,electrically coupled together in series, and defining a signal path foran RF signal. The wireless communications device also comprises a powerdetector coupled to an interior node in the signal path of themulti-stage amplifier. The power detector samples the RF signal at theinterior node, and provides a feedback signal to the baseband processor.Using the feedback signal, the baseband processor can adjust theamplification of the RF signal by the multi-stage amplifier, or canadjust the amplification of the RF signal by a preamplifier in thesignal path that provides the RF signal to the multi-stage amplifier.

[0015] These and other aspects of the present invention will become moreapparent through consideration of the accompanying drawings, and thefollowing detailed description, of the exemplary embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a block diagram of an embodiment of a multi-stageamplifier coupled with a power detector in accordance with the presentinvention;

[0017]FIG. 1A is a diagram of a conventional power detector that may beused in accordance with the present invention;

[0018]FIG. 1B is diagram of an alternative power detector that may beused in accordance with the present invention;

[0019]FIG. 2 is a schematic diagram of a simulated two-stage amplifier;

[0020]FIGS. 3A, 3B, and 3C are graphs of power detected versus actualpower at selected nodes of the simulated two-stage amplifier of FIG. 2;and

[0021]FIGS. 4 and 4A are simplified block diagrams of embodiments of aradio frequency transmission circuit in accordance with the presentinvention.

[0022] In the present disclosure, like objects that appear in more thanone figure are provided with like reference numerals.

DETAILED DESCRIPTION

[0023]FIG. 1 is a block diagram of an embodiment of a multi-stageamplifier 1 coupled with a power detector 2. An input node 3 ofmulti-stage amplifier 1 receives a signal that is to be amplified.Multi-stage amplifier 1 outputs the amplified signal at an output node11 of multi-stage amplifier 1. A signal path 4 for transmitting thesignal extends through multi-stage amplifier 1 between input node 3 andoutput node 11. In this example, the signal to be amplified bymulti-stage amplifier 1 is an RF signal, though signals having otherfrequencies could be used. Assume for the purpose of example that outputnode 11 is coupled to a load, and in particular to an antenna thatbroadcasts the RF signal output by multi-stage amplifier 1.

[0024] An input matching network 5 is coupled to input node 3 andprovides for proper matching of impedances between input node 3 and afirst amplifier stage 7. A node 5 a is in the signal path 4 within inputmatching network 5. First amplifier stage 7 has its input 7 a coupled toreceive the RF signal from input matching network 5. First amplifierstage 7 provides the amplified RF signal at its output 7 b, from whichthe RF signal passes to the input of an interstage matching network 8.Interstage matching network 8 provides for matching of impedancesbetween first amplifier stage 7 and a second amplifier stage 9. Node 8 ais in the signal path 4 within interstage matching network 8. Secondamplifier stage 9 receives the RF signal at its input 9 a frominterstage matching network 8, and outputs a further amplified RF signalat its output 9 b. Output 9 b of second amplifier stage 9 is coupled tooutput matching network 10. Output matching network 10 provides formatching of impedances between second amplifier stage 9 and the load,such as antenna 60, that is coupled to output node 11 of multi-stageamplifier 1. A node 10 a is in the signal path 4 within output matchingnetwork 10.

[0025] Input matching network 5, interstage matching network 8, andoutput matching network 10 may include inductors, capacitors, resistors,and other components common to impedance matching networks.

[0026] In the prior art, an input 2 a of the power detector 2 would becoupled to output node 11 of multi-stage amplifier 1 in order todetermine the output power of the signal being amplified by multi-stageamplifier 1 and provided to antenna 60.

[0027] We have found, however, that coupling power detector 2 to outputnode 11 provides a significant risk of underdetection of the power ofthe signal provided at output node 11. Therefore, in accordance with ourinvention, we couple power detector 2 not to output node 11, but ratherto an interior node, or a plurality of interior nodes, withinmulti-stage amplifier 1 on the signal path 4. The characteristics of theamplifier downstream of the point of sampling is known to the user ofoutput of power detector 2

[0028] Most broadly, the interior node is between, but exclusive of,input node 3 and output node 11 of multi-stage amplifier 1. This wouldinclude, for instance, connecting the power detector 2 to nodes 5 a, 7a, 7 b, 8 a, 9 a, 9 b, or 10 a on signal path 4, but would not includeconnecting power detector 2 to input node 3 or output node 11. In FIG.1, input 2 a of power detector 2 is shown coupled to the signal path 4at node 8 a. Node 8 a is within interstage matching network 8,downstream of the output 7 b of first amplifier stage 7. Detection atnodes 5 a or 7 a alone would require that the user of the detected powersignal, e.g., a baseband processor as in FIG. 4, has accurate knowledgeof the downstream characteristics of the amplifier. A signal reflectiveof the detected power at the interior node is provided by power detector2 at its output 2 b.

[0029] In a particular embodiment, input 2 a of the power detector 2 iscoupled to an interior node of multi-stage amplifier 1 that is betweeninput node 7 a of the first amplifier stage 7 and output node 11,exclusive of input node 7 a and output node 11. This embodiment wouldinclude, for instance, coupling power detector 2 to nodes 7 b, 8 a, 9 a,9 b, and 10 a on signal path 4, but would exclude coupling powerdetector 2 to node 5 a, input node 7 a or output node 11.

[0030] In a further embodiment, input 2 a of the power detector 2 iscoupled to an interior node of multi-stage amplifier 1 that is betweenoutput node 7 b of the first amplifier stage 7 and output node 11,exclusive of output node 11. This embodiment would include, forinstance, coupling power detector 2 to nodes 7 b, 8 a, 9 a, 9 b, and 10a along signal path 4, but would exclude coupling power detector 2 toinput node 5 a, input node 7 a, any nodes of first amplifier stage 7prior to output node 7 b, and output node 11.

[0031] In a further embodiment, input 2 a of the power detector 2 iscoupled to an interior node of multi-stage amplifier 1 in signal path 4that is between, and inclusive of, the output node 7 b of the firstamplifier stage 7 and the output node 9 b of the second amplifier stage9, but excludes nodes upstream or downstream of nodes 7 b and 9 b,respectively. This embodiment would include, for instance, couplingpower detector 2 to nodes 7 b, 8 a, 9 a, or 9 b along signal path 4, butwould exclude coupling power detector 2 to nodes 3, 5 a, 9 b, and 10 a.

[0032] In a further embodiment, input 2 a of the power detector 2 iscoupled to an interior node of multi-stage amplifier 1 in signal path 4that is between the output node 7 b of the first amplifier stage 7 andthe output node 9 b of the second amplifier stage 9, excluding outputnode 9 b. This embodiment would include, for instance, coupling powerdetector 2 to nodes 7 b, 8 a, or 9 a along signal path 4, but wouldexclude coupling power detector 2 to nodes 3, 5 a, 7 a, 9 b, and 10 a.

[0033] In a further embodiment, input 2 a of the power detector 2 iscoupled to an interior node of multi-stage amplifier 1 in signal path 4that is between, but exclusive of, the output node 7 b of the firstamplifier stage 7 and the output node 9 b of the second amplifier stage9. This embodiment would include, for instance, coupling power detector2 to nodes 8 a or 9 a in signal path 4, but would exclude coupling powerdetector 2 to nodes 3, 5 a, 7 a, 7 b, 9 b, and 10 a.

[0034] As a final exemplary embodiment, input 2 a of the power detector2 is coupled to an interior node of multi-stage amplifier 1 along signalpath 4 that is between output node 7 b of the first amplifier stage 7and the input node 9 a of the second amplifier stage 9. This embodimentwould include, for instance, coupling power detector 2 to nodes 7 b, 8a, or 9 a along signal path 4, but would exclude coupling power detector2 to nodes 3, 5 a, 7 a, 9 b, and 10 a.

[0035] In selecting an interior node at which to sample, one may wish toselect a node where there is a large voltage variation with power, butthat is relatively insensitive to mismatch.

[0036] Power detector 2 of FIG. 1 provides a feedback signal, e.g., a DCsignal, at its output 2 b that reflects the power of the signal on thesignal path 4 at the particular interior node being sampled by powerdetector 2. The feedback signal can be used to change the magnitude ofamplification by first amplifier stage 7 and/or second amplifier stage 9of multi-stage amplifier 1, among other possible uses.

[0037] Our coupling of power detector 2 to an interior node ofmulti-stage amplifier 1 on the signal path 4 that is upstream of outputnode 11, as opposed to the prior art approach that couples the powerdetector 2 to output node 11, can provide a more accurate determinationof the power of the amplified signal output by multi-stage amplifier 1.Specifically, impedance changes at output node 11 due to changes in theload impedance, e.g., when the antenna is brought into contact with anobject, will have a lesser effect on power detector 2 when powerdetector 2 is coupled in accordance with our invention than when thepower detector 2 is coupled to output node 11. Simulation datasupporting these and other conclusions is provided below with respect toFIGS. 2, 3A, 3B, and 3C.

[0038] Practitioners will appreciate that multi-stage amplifier 1 ofFIG. 1 is illustrated at a high level, and that it would apply tonumerous specific amplifier implementations.

[0039]FIG. 2 shows a simulated two-stage, 800 MHz, +28 dBm poweramplifier 28. The amplifier 28 includes a first bipolar transistor 30,an interstage matching network 32, and a second bipolar transistor 34through which a signal path 36 extends. First and second bipolartransistors 30, 34 amplify a signal (here an RF signal) that is inputonto the signal path 36 at the gate of first bipolar transistor 30.

[0040] Amplifier 28 includes three nodes where a voltage sample is takenby a power detector. The three nodes are: (1) a first stage node 38 atthe collector (i.e., output) of first bipolar transistor 30; (2) aninterstage node 40 within matching network 32; and (3) a second stagenode 42 at the collector (i.e., output) of second bipolar transistor 34.

[0041] Interstage matching network 32 in this simulated circuit consistsof a first series capacitor 32 a coupled between the collector of firsttransistor 30 (node 38) and interstage node 40; a shunt inductor 32 bcoupled between interstage node 40 and ground; and a second seriescapacitor 32 c coupled between interstage node 40 and the base of secondbipolar transistor 34. Inductors 43 and 44 are coupled to nodes 38 and42, respectively, as input and output matching networks.

[0042] For the simulated circuit of FIG. 2, the range of error where thedetected power is lower than the actual output power is between 4 dB and0.8 dB depending on which of nodes 38, 40, or 42 is sampled, as shown inFIGS. 3A, 3B, and 3C, respectively.

[0043]FIGS. 3A, 3B, and 3C illustrate the variance of the voltage atnodes 38, 40, and 42, respectively, of FIG. 2 as a function of theactual output power of amplifier 28 for impedance mismatches at VoltageStanding Wave Ratios (VSWR) of 1:1, 1.5:1, 2:1, 3:1, 6:1, and 10:1.

[0044] With respect to FIG. 3A, it can be seen that, when a powerdetector is coupled to node 38, the maximum underdetection error is 3.0dB or a 100% under detection. With respect to FIG. 3B, it can be seenthat when a power detector is coupled to node 40, the maximumunderdetection error is 0.7 dB or a 17% under detection. With respect toFIG. 3C, it can be seen that when a power detector is coupled to node42, the maximum underdetection error is 3.6 dB or a 130% underdetection.

[0045] Thus, from the data of FIG. 3C, one can see that, for thesimulated multi-stage amplifier 28 of FIG. 2, the least favorable place,in terms of the amount of possible underdetection error, to couple apower detector to the signal path 36 is at the output of the finalamplifier stage 34, i.e., at node 42. From the data of FIG. 3A, one cansee that, for the simulated amplifier 28 of FIG. 2, a better place tocouple a power detector to the signal path 36, in terms of the amount ofpossible underdetection error, is at node 38 at the output of the firstamplifier stage 30. Finally, from the data of FIG. 3B, a still betterplace to couple a power detector to the signal path 36, in terms of theamount of possible underdetection error, is at node 40 within interstagenetwork 30, which is between the output of the first amplifier stage 30and the input of the second amplifier stage 34.

[0046] With respect to the multi-stage amplifier 1 of FIG. 1, the dataof FIGS. 2, 3A, 3B, and 3C counsels against the coupling of powerdetector 2 to the signal path 4 at the output node 11 of multi-stageamplifier 1, due to the relatively great amount of underdetectionpossible in an impedance mismatch condition. As mentioned above, itwould be better to couple power detector 2 to an interior node ofamplifier 1 that is inward of, and exclusive of, input node 3 and outputnode 11. Coupling the power detector 2 to node 8 a is expected to yieldthe lowest amount of underdetection error.

[0047] In the embodiment of FIG. 1, a multi-stage amplifier 1 with twostages is depicted. In a case where multi-stage amplifier 1 has morethan two stages, a power detector 10 can be coupled to any interior nodein the signal path through the multi-stage amplifier. For instance, in amulti-stage amplifier with three stages, the power detector 2 could becoupled to the signal path between the first and second amplifiers, orbetween the second and third amplifier stages.

[0048] The configuration of power detector 2 and its means of couplingto signal path 4 at the selected interior node of multi-stage amplifier1 of FIG. 1 can vary.

[0049] For instance, in FIG. 1A, a block diagram of a conventionalSchottky diode power detector is depicted as an example of powerdetector 2. As mentioned above, an input 2 a of power detector 2 iscoupled to an interior node of multi-stage amplifier 1, e.g., node 8 a,of FIG. 1. A capacitor 15 is provided at input 2 a in order to provideAC coupling. Capacitor 15 also is coupled to an input of a diode 16.Diode 16 that provides half-wave rectification. The output of diode 16is coupled to a non-inverting input 17 a of an operational amplifier 17.The inverting input 17 b of operational amplifier 17 is coupled to itsoutput 17 c. The output of operational amplifier 17 is provided to theoutput 2 b of power detector 2. Temperature compensation circuit 19provides additional or reduced bias to the input signal in order tocompensate for temperature. Temperature compensation 19 circuit can be aknown temperature compensation circuit. Bias circuit 18 may be coupledto the inverting input 17 b of operational amplifier 17.

[0050] In an alternative embodiment, a power detector is coupled to aplurality of interior nodes of multi-stage amplifier 1, and a signalreflective of the power at those plural interior nodes is generated.Sampling a plurality of interior nodes of multi-stage amplifier, andsumming the detected voltages can potentially provide more accuratepower detection. The number of interior nodes sampled can vary.

[0051] For instance, in FIG. 1B, a multiple node power detector 200 isshown. Power detector 200 includes a plurality of power detectors 2, onefor each of the interior nodes of the multi-stage amplifier 1 that arebeing sampled. In this example, power detector 200 includes two powerdetectors 2. Each power detector 2 includes an input 2 a, a couplingcapacitor 15, a half-wave rectifying diode 16, and a temperaturecompensation circuit 19, as described above for FIG. 1A. The respectiveinputs 2 a are each coupled to a different one of the plural interiornodes being sampled, e.g., one to node 8 a and one to amplifier output 9b. A summing amplifier 23 is coupled to the output of each of the diodes16. Summing amplifier 23 includes resistors R1, R2, and R3, and anoperational amplifier 24. Each of resistors R1 and R2 is coupled betweenthe output of the diode 16 and the inverting input 24 b of operationalamplifier 24. The non-inverting input 24 a of operational amplifier 24is coupled to ground. Resistor R3 is coupled between the output 24 c ofoperational amplifier 24 and the inverting input 24 b of operationalamplifier 24. Summing amplifier 23 sums the respective signal outputs ofthe respective power detectors 2, and outputs a sum signal (e.g., a DCvoltage) that reflects the power at the plural interior nodes beingsampled. The ratio of the values of resistors R1 and R2 determines theweight that will be accorded to the respective interior nodes in theoutput of summing amplifier 23. For instance, if R1=R2, then equalweight is accorded to the two interior nodes being sampled by multiplenode power detector 200. On the other hand, if R1<R2, then greaterweight would be given to the sample passed through the power detector 2that includes R2. Such unequal weighting may be desirable where oneinterior node provides relatively more useful data.

[0052] While a particular summing amplifier 23 is provided in theexemplary circuit of FIG. 1B, any other known circuits capable ofsumming the outputs of the plural power detectors 2 may be used. Inaddition, instead of using a summing circuit, other circuits may becoupled to the output of the diodes 16, to create a different type ofsignal reflective of the detected power at the plural interior nodes.For instance, a differential signal may be produced. That is, in placeof summing amplifier 23, a differential amplifier 23 may be used thatdetermines a difference between the signal outputs of the respectivepower detectors 2, and outputs a differential signal that reflects theoutput power.

[0053] Referring to FIG. 4, a simplified block diagram of an embodimentof a radio frequency transmission circuit 50 of a wirelesscommunications device, e.g., a cellular phone, is illustrated. Radiofrequency transmission circuit 50 may be implemented on a singleintegrated circuit, or may be implemented in an integrated circuit thatis coupled to external, discrete components.

[0054] In radio transmission circuit 50, a baseband processor 54receives data, which may be voice data and/or packet data, at an inputnode 52 on signal path 4. Baseband processor 54 may further process thedata, and then outputs the data onto the signal path 4. Based on aspecified modulation standard, a modulator 56 modulates the data toproduce an RF modulated signal. A filter 58 provides a filtered outputof the modulated signal to input node 3 of multi-stage amplifier 1 (seeFIG. 1). Multi-stage amplifier 1 amplifies the modulated signal togenerate an amplified RF signal, which is sent via output node 11 toantenna 60 for broadcasting.

[0055] In accordance with the present invention, power detector 2 ofFIG. 1A is coupled to multi-stage amplifier 1 at a node in the signalpath 4 upstream of output node 11. In this particular embodiment, powerdetector 2 is coupled to the signal path 4 at node 8 a, as was shown inFIG. 1. Note that multi-stage amplifier 1 may have more than twoamplifier stages, and that power detector 2 could be coupled the signalpath 4 at an interior node between any of the amplifier stages.

[0056] Power detector 2 outputs a feedback signal (e.g., a DC voltage)at its output 2 b that is provided to baseband processor 54 on line 62.The feedback signal is indicative of the power of the RF signal sampledat node 8 a of the signal path 4 (i.e., after the output of firstamplifier stage 7 and before the input of second amplifier stage 9).Based on the magnitude of the feedback signal provided by power detector2, baseband processor 54 then can adjust the magnitude of amplificationby amplifier 1 by providing a control signal to multi-stage amplifier 1on line 64. For instance, the magnitude of amplification provided to theRF signal by multi-stage amplifier 1 can be adjusted by changing areference voltage that is being provided to a DC bias circuit (notshown) for multi-stage amplifier 1. Baseband processor 54 accounts forcharacteristics of multi-stage amplifier 1 downstream of the sampledinterior node using, for instance, stored values in memory, software,and/or firmware.

[0057] In an alternative embodiment shown in FIG. 4A, a preamplifier 66is provided in signal path 4 between filter 58 and multi-stage amplifier1. Baseband processor 54 is coupled to the preamplifier 66 by line 68.Baseband processor 54 can provide a control signal on line 68 topreamplifier 66 to adjust an amount of amplification of the RF signal onsignal path 4 upstream of multi-stage amplifier 1. For instance, thecontrol signal can adjust a DC bias current provided to the preamplifier66 to change its amount of amplification of the RF signal. Accordingly,the RF signal provided on signal path 4 to input node 3 of multi-stageamplifier 1 will have a magnitude that will allow multi-stage amplifier1 to amplify the RF signal to the desired power level. In determiningthe control signal provided to preamplifier 66, baseband processor 54must account for the expected amount of amplification to be provided tothe RF signal by multi-stage amplifier 1.

[0058] In a further alternative embodiment that combines aspects ofFIGS. 4 and 4A, baseband processor 54 may be coupled both topreamplifier 66 and to multi-stage amplifier 1, and may selectivelycontrol either or both of preamplifier 66 and multi-stage amplifier 1based on the feedback signal provided by power detector 2.

[0059] In an alternative embodiment, power detector 200 of FIG. 1B maybe coupled to multi-stage amplifier 1 of FIGS. 4 and 4A, so that thepower of the RF signal at a plurality of interior nodes on signal path 4within multi-stage amplifier 1 may be detected. As mentioned, powerdetector 200 outputs a voltage that is a sum of the respective voltagesamples taken at each of the plural interior nodes being sampled. Theoutput of power detector 200 at its output 2 b may then be fed tobaseband processor 54 over line 62 for the purpose of adjustingmulti-stage amplifier 1 and/or preamplifier 60.

[0060] Radio frequency transmission circuit 50 may operate according toany number of communication standards, including, but not limited to,the CDMA, WCDMA, Global System for Mobile Communications (OSM), and theAdvanced Mobile Phone Service (AMPS) standards. Further, radio frequencytransmission circuit 50 can be included in a device that both receivesand transmits radio frequency signals, such as a battery-poweredcellular phone.

[0061] The circuits and methods of the present application may beincorporated together in a single integrated circuit, or provided onplural coupled integrated circuits, made with silicon, silicongermanium, gallium arsenide, or other process technologies. Also, thecomponents described herein can be a combination of integratedcircuit(s) and discrete components.

[0062] Other circuits and systems in related technological areas aredepicted and described in U.S. Provisional Patent Application No.60/418,816, filed Oct. 15, 2002, entitled “A Continuous Bias PowerAmplifier,” and 60/419,027, filed Oct. 15, 2002, entitled “AnAutomatically Biased Power Amplifier,” both of which are incorporatedherein by reference in their respective entireties.

[0063] The detailed description provided above is merely illustrative,and is not intended to be limiting. While embodiments, applications andfeatures of the present inventions have been depicted and described,there are many more embodiments, applications and features possiblewithout deviating from the spirit of the inventive concepts describedand depicted herein.

What is claimed is:
 1. An amplifier power detection circuit comprising:an amplifier comprising plurality of amplifier stages coupled in seriesbetween an input node and an output node of the amplifier, wherein asignal path extends through the plurality of amplifier stages betweenthe input node and the output node of the amplifier; an interior node onthe signal path within the amplifier located between, but not including,the input node and the output node; and a power detector comprising aninput coupled to the interior node, said power detector capable ofsampling a first signal on the signal path at the interior node andoutputting a second signal reflective of a power of the first signal. 2.The amplifier power detection circuit of claim 1 further comprising atleast one intermediate said amplifier stage coupled along the signalpath between a first said amplifier stage and a final said amplifierstage of the amplifier, wherein the interior node is between either thefirst amplifier stage and the at least one intermediate amplifier stageor between the at least one intermediate amplifier stage and the finalamplifier stage.
 3. The amplifier power detection circuit of claim 1further comprising at least two intermediate said amplifier stagescoupled between a first said amplifier stage and a final said amplifierstage of the amplifier, wherein the input of the power detector iscoupled to the interior node between the at least two intermediateamplifier stages.
 4. The amplifier power detection circuit of claim 1further comprising a matching network coupled between respective ones ofthe plural amplifier stages, wherein the interior node comprises a nodewithin the matching network.
 5. The amplifier power detection circuit ofclaim 1, wherein the interior node is between the output of a first saidamplifier stage and an output of a final said amplifier stage of theamplifier, exclusive of the output of the final amplifier stage.
 6. Theamplifier power detection circuit of claim 1, wherein the interior nodeis between the output of a first said amplifier stage and an input of afinal said amplifier stage.
 7. The amplifier power detection circuit ofclaim 6, further comprising a matching network between the firstamplifier stage and the final amplifier stage, wherein the interior nodeis on the signal path within the matching network
 8. The amplifier powerdetection circuit of claim 1 further comprising a matching networkcoupled between the final amplifier stage and the output node, whereinthe internal node is within the matching network.
 9. The amplifier powerdetection circuit of claim 1 wherein the power detector and theplurality of amplifier stages are entirely formed on a single integratedcircuit.
 10. The amplifier power detection circuit of claim 1, furthercomprising: a second interior node on the signal path within theamplifier and located between, but not including, the input node and theoutput node of the amplifier; a second power detector coupled to thesecond interior node, said second power detector capable of sampling thefirst signal at the second interior node and outputting a third signalreflective of a power of the first signal at the second interior node; afirst circuit coupled to receive the second and third signals, andcapable of outputting a fourth signal derived from the second and thirdsignals.
 11. The amplifier power detection circuit of claim 10, whereinthe first circuit comprises a summing circuit that sums the second andthird signals to create the fourth signal.
 12. The amplifier powerdetection circuit of claim 10, wherein the first circuit comprises adifference circuit the creates a difference between the second and thirdsignals to create the fourth signal.
 13. A method for detecting anoutput power of a multi-stage amplifier that comprises a plurality ofamplifier stages, an input node, and an output node, with a signal pathextending from the input node to the output node through the pluralityof amplifier stages, the method comprising: detecting a first signal atan interior node of the amplifier, said interior node being in thesignal path within the multi-stage amplifier, exclusive of the inputnode and the output node; and providing a second signal reflective of apower of the first signal at the interior node.
 14. The method of claim12 wherein the multi-stage amplifier includes at least a first saidamplifier stage, an intermediate said amplifier stage, and a final saidamplifier stage coupled in series on the signal path, and the interiornode is between the first and intermediate amplifier stages, or theintermediate and final amplifier stages.
 15. The method of claim 12,further comprising varying a reference voltage provided to a biascircuit that biases the amplifier based upon the second signal.
 16. Themethod of claim 12, further comprising adjusting a degree ofamplification of the first signal by the amplifier based on the secondsignal.
 17. The method of claim 12, further comprising adjusting amagnitude of the first signal in response to the second signal at apoint prior to the input node of the multi-stage amplifier.
 18. Themethod of claim 12, wherein the interior node is between the output of afirst said amplifier stage and an output of a final said amplifierstage, exclusive of the output of the final amplifier stage.
 19. Themethod of claim 12, wherein the interior node is between the output of afirst amplifier stage and an input of a final amplifier stage.
 20. Themethod of claim 18, further comprising a matching network within themulti-stage amplifier between the first amplifier stage and the finalamplifier stage, wherein the interior node is on the signal path withinthe matching network
 21. The method of claim 12, further comprising:detecting the first signal at a second interior node of the multi-stageamplifier, said second interior node being on the signal path within themulti-stage amplifier, exclusive of the input node and the output node;providing a third signal reflective of a power of the first signal atthe second interior node; and using the second and third signals tocreate a fourth signal.
 22. The method of claim 20, wherein in summingthe second and third signals, a greater weight is given to one or theother of the second and third signals.
 23. A wireless communicationsdevice comprising: a processor; an antenna; a signal path between theprocessor and the antenna; an amplifier comprising a plurality ofamplifier stages in the signal path between the processor and theantenna, said amplifier including an interior node in the signal pathbetween, and exclusive of, an input node of the amplifier that receivesa first signal on the signal path and an output node of the amplifierfrom which the first signal goes to the antenna; a power detector havingan input coupled to the interior node and an output coupled to theprocessor, wherein the power detector is operable to detect the firstsignal at the interior node and to provide a second signal to theprocessor reflective of a power of the first signal at the interiornode, and the processor is operable to adjust an amplitude of the firstsignal in response to the second signal.
 24. The wireless communicationsdevice of claim 22, wherein the processor is coupled to the amplifier,and the processor operates to adjust an amplitude of the first signal byadjusting an amount of amplification of the first signal by theamplifier.
 25. The wireless communications device of claim 22, whereinthe processor operates to adjust the amplitude of the first signal byvarying a reference voltage provided to a bias circuit that biases theamplifier.
 26. The wireless communications device of claim 22, whereinthe processor is coupled to a preamplifier in the signal path betweenthe processor and the input node of the amplifier, and the processoroperates to adjust the amplitude of the first signal by adjusting anamount of amplification of the first signal by the preamplifier prior tothe signal reaching the input node of the amplifier.
 27. The wirelesscommunications device of claim 22, wherein the amplifier includes atleast a first said amplifier stage and a final said amplifier stagecoupled in series on the the signal path, and the interior node isbetween the an output of the first amplifier stage and an input of thefinal amplifier stage.
 28. The wireless communications device of claim22 wherein the amplifier includes at least a first said amplifier stage,an intermediate said amplifier stage, and a final said amplifier stagecoupled in series on the signal path, and the interior node is betweenthe first and intermediate amplifier stages, or the intermediate andfinal amplifier stages.
 29. The wireless communications device of claim22, wherein the interior node is within a matching network that isdisposed within the amplifier on the signal path between a first saidamplifier stage and a final said amplifier stage of the amplifier. 30.The wireless communication device of claim 22 wherein the power detectorand the amplifier are entirely formed on a single integrated circuit.31. A wireless communications device, comprising: a processor; anantenna; a signal path between the processor and the antenna; anamplifier comprising a plurality of amplifier stages in the signal pathbetween the processor and the antenna, said amplifier including aplurality of interior nodes in the signal path between, and exclusiveof, an input node of the amplifier that receives a first signal on thesignal path and an output node of the amplifier from which the firstsignal goes to the antenna; a power detector comprising a plurality ofinputs and an output, wherein each said the input is coupled to aseparate one of the interior nodes, the power detector is operable todetect the first signal at the respective interior node, and the powerdetector is operable to output a second signal that reflects a power ofthe first signal at the plurality of interior nodes, and wherein theprocessor is operable to adjust an amplitude of the first signal inresponse to the second signal.
 32. The wireless communications device ofclaim 30, wherein the processor is coupled to the amplifier, and theprocessor operates to adjust an amplitude of the first signal byadjusting an amount of amplification of the first signal by theamplifier.
 33. The wireless communications device of claim 30, whereinthe processor operates to adjust the amplitude of the first signal byvarying a reference voltage provided to a bias circuit that biases theamplifier.
 34. The wireless communications device of claim 30, whereinthe processor is coupled to a preamplifier in the signal path betweenthe processor and the input node of the amplifier, and the processoroperates to adjust the amplitude of the first signal by adjusting anamount of amplification of the first signal by the preamplifier prior tothe signal reaching the input node of the amplifier.
 35. The wirelesscommunications device of claim 30, wherein the amplifier includes atleast a first said amplifier stage and a final said amplifier stagecoupled in series on the signal path, and at least one detected saidinterior node is between an output of the first amplifier stage and aninput of the final amplifier stage.
 36. The wireless communicationsdevice of claim 30 wherein the amplifier includes at least a first saidamplifier stage, an intermediate said amplifier stage, and a final saidamplifier stage coupled in series on the signal path, and one saiddetected interior node is between the first and intermediate amplifierstages, and another said detected interior node is between intermediateand final amplifier stages.
 37. The wireless communications device ofclaim 30, wherein at least one said interior node is within a matchingnetwork that is disposed within the amplifier on the signal path betweena first said amplifier stage and a final said amplifier stage of theamplifier.
 38. The wireless communications device of claim 30, whereinthe second signal is a sum of respective signals derived from respectivesaid interior node.